module yt_data_rec(
		input	wire		resetb,
		input	wire		sclk,
		
		input	wire		mac_flag,
		input	wire	[7:0]	mac_data,       
		input	wire		mac_error,
		input	wire	[1:0]	mac_vendor,//0:无效包 1：中庆 2：YT
		input	wire		yt_vs_pre,
		
		input	wire	[11:0]	l_start_byte,
		input	wire	[11:0]	l_end_byte,
		input	wire	[11:0]	h_start,
		input	wire	[11:0]	h_end,
		
		output	reg		vsout,
		output	reg		rec_hout,
		output	reg	[7:0]	rec_dout,
		output	reg	[11:0]	l_num,
		output	reg	[11:0]	h_num,
		
		output	reg	[7:0]	yt_depth,
		output	reg	[11:0]	yt_l_total_byte
		
		);

/************************************************/
//		信号定义
/************************************************/
parameter Preamble_OFFSET	=45;
parameter CARD_NUM_LOW		=47-Preamble_OFFSET;
parameter CARD_NUM_HIGH		=48-Preamble_OFFSET;
parameter PACK_TYPE_FIRST	=49-Preamble_OFFSET;
parameter PACK_TYPE_SECOND	=50-Preamble_OFFSET;
parameter REMAINDER_HNUM	=51-Preamble_OFFSET;//一行包内剩余的显示数据行数
parameter YT_DEPTH		=52-Preamble_OFFSET;//端口参数起始

reg	[6:0]	mac_count;
reg	[15:0]	card_num;
wire	[11:0]	start_h;
reg		data_en_pre;
reg	[7:0]	portnum_in_h;
reg		port_info_flag,port_info_flag_t;
reg	[1:0]	port_info_cnt;
reg	[10:0]	data_count;
reg	[15:0]	port_pre;
wire	[4:0]	port_num;
reg	[4:0]	port_num_t;
reg	[11:0]	yt_l_total_byte_t;
wire	[10:0]	start_num;
reg	[10:0]	port_num_max;
reg	[11:0]	l_count;
reg	[11:0]	h_count;
reg		hout_t1;
reg	[7:0]	dout_t1;
reg	[7:0]	yt_depth_t; 
/************************************************/
//		数据计数
/************************************************/

always	@(posedge sclk)
	if (mac_flag==0)
		mac_count<=0;
	else if (mac_count[6]==0)
		mac_count<=mac_count+1;
		
/************************************************/
//		帧包处理
/************************************************/
always	@(posedge sclk)
	if (mac_flag==0)
		vsout<=0;
	else if (mac_count==PACK_TYPE_SECOND && mac_data==8'h13 && mac_vendor==2 && yt_vs_pre==0)	//UDP
		vsout<=1;

/************************************************/
//	行包处理
/************************************************/
always	@(posedge sclk or negedge resetb)
	if(!resetb)
		card_num<=0;
	else if(mac_vendor==2)
		case (mac_count)
			CARD_NUM_LOW:card_num[7:0]<=mac_data;
			CARD_NUM_HIGH:card_num[15:8]<=mac_data;
		endcase

assign start_h={card_num[8:0],3'b0}-8;


always	@(posedge sclk)
	if (mac_flag==0)
		data_en_pre<=0;
	else if (mac_count==PACK_TYPE_SECOND && mac_data==8'h05 && mac_vendor==2)	
		data_en_pre<=1;


always	@(posedge sclk or negedge resetb)
	if(!resetb)
		portnum_in_h<=0;
	else if (data_en_pre==1 && mac_count==REMAINDER_HNUM)	//一个行包中还剩余的行数
		portnum_in_h<=mac_data;
	else if(port_info_flag==1 && port_info_flag_t==0)
		portnum_in_h<=portnum_in_h-1;

always	@(posedge sclk or negedge resetb)
	if(!resetb)
		port_info_flag<=0;
	else if(data_en_pre==1 && mac_count==YT_DEPTH)
		port_info_flag<=1;
	else if(data_en_pre==1 && data_count==1 && portnum_in_h>0 && port_info_flag==0)
		port_info_flag<=1;
	else if(port_info_cnt==3)
		port_info_flag<=0;
		
always	@(posedge sclk)
	if(port_info_flag==0)
		port_info_cnt<=0;
	else
		port_info_cnt<=port_info_cnt+1;

always	@(posedge sclk)
	port_info_flag_t<=port_info_flag;


always	@(posedge sclk or negedge resetb)
	if(!resetb)
	begin
		port_pre<=0;
		port_num_max<=0;
	end
	else if(port_info_flag==1)
		case(port_info_cnt)
			0:	port_pre[7:0]<=mac_data;
			1:	port_pre[15:8]<=mac_data;
			2:	port_num_max[7:0]<=mac_data;	
			3:	port_num_max[10:8]<=mac_data[2:0];	
		endcase

assign	port_num=port_pre[15:11];
assign	start_num=port_pre[10:0];

always	@(posedge sclk or negedge resetb)
	if(!resetb)
	begin
		h_count<=0;
		l_num<=0;
	end
	else if(port_info_cnt==3)
	begin
		h_count<=start_h+port_num;
		l_num<=start_num;
	end

always	@(posedge sclk or negedge resetb)
	if(!resetb)
		data_count<=0;
	else if(data_en_pre==0)
		data_count<=0;
	else if(port_info_flag_t==1 && port_info_flag==0)
		data_count<=port_num_max-1;
	else if(data_count!=0)
		data_count<=data_count-1;

always	@(posedge sclk or negedge resetb)
	if(!resetb)
		hout_t1<=0;
	else if(mac_flag==0)
		hout_t1<=0;
	else if(port_info_flag==0 && port_info_flag_t==1)
		hout_t1<=1;
	else if(port_info_flag==1 && port_info_flag_t==0)
		hout_t1<=0;
	else if(data_count==0)
		hout_t1<=0;

always	@(posedge sclk)
begin
	dout_t1<=mac_data;
	rec_dout<=dout_t1;
end

always	@(posedge sclk or negedge resetb)
	if(!resetb)
		l_count<=0;
	else if(hout_t1==0)
		l_count<=l_num;
	else
		l_count<=l_count+1;

always	@(posedge sclk or negedge resetb)
	if(!resetb)
		rec_hout<=0;
	else if(l_count>=l_start_byte && l_count<l_end_byte && hout_t1==1 && h_count>=h_start && h_count<h_end)
		rec_hout<=1;
	else
		rec_hout<=0;

always	@(posedge sclk or negedge resetb)
	if(!resetb)
		h_num<=0;
	else
		h_num<=h_count-h_start; 
/************************************************/
//	解析级联号
/************************************************/
always	@(posedge sclk or negedge resetb)
	if(resetb==0)
		yt_depth_t<=0;
	else if (data_en_pre==1 && mac_count==YT_DEPTH)
		yt_depth_t<=mac_data;
		
always	@(posedge sclk or negedge resetb)
	if(resetb==0)
		yt_depth<=0;
	else if(mac_flag==0 && mac_error==0)
		yt_depth<=yt_depth_t-1;	//接收卡1为0，接收卡2为1……

always	@(posedge sclk)
	port_num_t<=port_num;
	
always	@(posedge sclk or negedge resetb)
	if(resetb==0)
		yt_l_total_byte_t<=0;
	else if(hout_t1==0 && rec_hout==1)
		yt_l_total_byte_t<=l_count;

always	@(posedge sclk or negedge resetb)
	if(resetb==0)
		yt_l_total_byte<=0;
	else if(port_num_t!=port_num)
		yt_l_total_byte<=yt_l_total_byte_t;// l_count+1;
endmodule		

